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DATA SHEET
Part No. Package Code No.
MN662793
LQFP100-P-1414
SEMICONDUCTOR COMPANY MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Publication date: December. 2004
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MN662793 Contents
Overview ............................................................................................................................. 3 Features ............................................................................................................................. 3 Applications ........................................................................................................................ 4
Application Circuit ................................................................................................................. 5 Block Diagram .................................................................................................................... 6
Pin Assignment .................................................................................................................... 7 Pin Descriptions .................................................................................................................... 8
Absolute Maximum Ratings ..................................................................................................... 12 Operating Supply Voltage Range............................................................................................... 13 Electrical Characteristics ........................................................................................................ 15
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MN662793
Silicon CMOS IC
Overview
Features
(Optical Servo) Focus, tracking, and traverse servos Automatic adjustment functions (Focus / Tracking gain, Focus / Tracking offset, Focus / Tracking balance) Provided with a countermeasure for dropout Provided with an anti-shock detection function Provided with a track-cross function Drive output PWM drive function supported Provided with supply voltage monitoring and a servo gain automatic adjustment function (Digital Signal Processing) Containing DSL and analog / digital PLL Provided with a frame synchronous detection / protection / interpolation Subcode data processing Q-data CRC check On-chip Q-data register On-chip CD-TEXT data register CIRC error correction C1 decoder: double error correction C2 decoder: triple / quadruple error correction On-chip deinterleaving 16-K RAM CD-ROM error correction Q decoder: an error correction P decoder: an error correction Mode1 and Mode 2 compatible Audio data interpolation processing 4-sampling average value interpolation and previous value hold (Spindle Motor Servo) CLV digital servo Servo gain setting function Shaft loss compensation setting function (Audio Circuit) Soft muting Digital attenuation (2048 levels) Soft attenuation (2048 levels) Digital audio interface (EIAJ format) 8 x -oversampling digital filter On-chip low-voltage OP amp Bass boost filter, high-band notch filter, and surround function On-chip digital de-emphasis
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Features (continued)
(MP3 Decoding) Decoding of asignals recorded in MPEG1-layer3 or MPEG2-layer3 format Decoding of asignals recorded in MPEG1-layer2 or MPEG2-layer2 format Decoding of asignals recorded in MPEG2.5 format Sampling rate conversion from signals recorded at Fs = 32 kHz or 48 kHz to 44.1 kHz (WMA Decoding) Decoding of signals recorded in WMA Ver. 8 format (Sampling rate: 48 kHz to 22.05 kHz) Supporting special playback (forward, reverse, and resume playback) (SD Interface) Stream serial input from SD available (Anti-shock Memory Controller) ADPCM 4-bit compression or expansion / decompression in full-bit (16 bits) mode External DRAM selectable Async DRAM (Data bus width: 4 bits) 64M-bit DRAM x 1 16M-bit DRAM x 2 16M-bit DRAM x 1 + 4M-bit DRAM x 1 16M-bit DRAM x 1 4M-bit DRAM x 2 4M-bit DRAM x 1 1M-bit DRAM x 2 1M-bit DRAM x 1 Async DRAM (Data bus width: 16 bits) 128M-bit DRAM x 1 64M-bit DRAM x 1 16M-bit DRAM x 1 4M-bit DRAM x 1 SDRAM (Data bus width: 16 bits) 128M-bit DRAM x 1 64M-bit DRAM x 1 16M-bit DRAM x 1 4M-bit DRAM x 1 (Others) Disc rotation mechanism has a synchronous playback (jitter-free) mode (- 50 % to + 50 %) 8 x -speed playback (when using jitter-free function) TX output (1 x -, 2 x -, 3 x-and 4 x-speed) supported Serial data output pitch shift function A patent license must be acquired from the management company when using MPEG Layer3 products.
Applications
Signal processing LSI for CDs (Compact Discs)
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D/A Converter
Application Circuit
DRVDD
IOVDD
LOVDD2
AVDD
LOVDD1
100 pF 15 1 k + 47 k 100 pF 1.5 k 2.2 k 0.001 F + 47 k 47 k 22 F 560 22 F
DRVDD1, 2 AVDD
IOVDD1, 2
LOVDD2
0.0018 F 47 k
OUTL LOVDD1
SDD00031AEM
MN6627932CF LOVSS1
+ -
0.1 F
100 F
OUTR
100 pF 22 F
DVSS1, 2, 3
LOVSS2
AVSS
1 k +
47 k
47 k +
22 F 560
0.0018 F 47 k
100 pF 1.5 k 2.2 k 0.001 F
47 k
DVSS
LOVSS2
AVSS
LOVSS1
5
MN662793
Block Diagram
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MN662793
Pin Arrangement
Note) Pins marked with an asterisk can be switched to different signals by using microcontroller commands.
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Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Symbol D11 D10 D9 D8 UDQM SDRCK A11 A9 A8 A7 A6 A5 A4 LDQM NWE NCAS NRAS NCS A3 A2 A1 A0 DRVDD1 DVSS1 A10
*BA1 *BA0
I/O I/O I/O I/O I/O O O O O O O O O O O O O O O O O O O I I O O O I O O O DRAM data signal I/O 11 DRAM data signal I/O 10 DRAM data signal I/O 9 DRAM data signal I/O 8
Function
SDRAM upper byte data mask signal output SDRAM clock signal output DRAM address signal output 11 DRAM address signal output 9 DRAM address signal output 8 DRAM address signal output 7 DRAM address signal output 6 DRAM address signal output 5 DRAM address signal output 4 SDRAM lower byte data mask signal output DRAM write enable signal output DRAM CAS control signal output DRAM RAS control signal output SDRAM chip select signal output DRAM address signal output 3 DRAM address signal output 2 DRAM address signal output 1 DRAM address signal output 0 Power supply 1 for DRAM interface I/O Ground 1 for digital circuits DRAM address signal output 10 SDRAM bank selection signal output 1 SDRAM bank selection signal output 0 Power supply 1 for internal digital circuits Spindle drive signal output (absolute value) Spindle drive signal output (polarity) Traverse drive signal output (positive polarity)
DVDD1 SPOUT
*SPPOL
TRVP
Note) Pins marked with an asterisk can be switched to different signals by using microcontroller commands. The specifications of the DRAM pins depend on their type and capacitance.
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Pin Descriptions (continued)
Pin No. 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 Symbol
*TRVM *TRVP2 *TRVM2
I/O O O O O O O O I O O I I I I O I I I I I I O I O O I O I O I I O
Function Traverse drive signal output (negative polarity) Traverse drive signal output 2 (positive polarity) Traverse drive signal output 2 (negative polarity) Tracking drive signal output (positive polarity) Tracking drive signal output (negative polarity) Focus drive signal output (positive polarity) Focus drive signal output (negative polarity) Power supply 1 for digital I/O Tracking balance adjustment signal output Focus balance adjustment signal output Focus error signal input Tracking error signal input Voltage input for supply voltage monitor RF envelope signal input Laser ON signal output RF detection signal input Off-track signal input Dropout signal input Power supply for analog circuits Analog reference current input RF signal input DSL loop filter pin PWM output mode selection input Low: Direct High: 3-state PLL loop filter pin (for phase comparison output) PLL loop filter pin (for speed comparison output) Ground for analog circuits L-ch. audio output for line-out output Ground for line-out output R-ch. audio output for line-out output Power supply for line-out output Test mode setting input (L fix) Test monitor output 1
TRP
*TRM
FOP
*FOM
IOVDD1 TBAL FBAL FE TE ADPVCC RFENV LDON NRFDET OFT BDO AVDD IREF ARF DSLF PWMSEL PLLF PLLFO AVSS LOOUTL LOVSS1 LOOUTR LOVDD1 NTEST2 TMON1
Note) Pins marked with an asterisk can be switched to different signals by using microcontroller commands.
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Pin Descriptions (continued)
Pin No. 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 Symbol LOVDD2 LOVSS2 TMON2 DVDD3 DVSS2
*EXT0 *
I/O I I O I I I/O I/O I/O I I I O O O O O O I I I I O I I I/O I/O I/O I/O I/O I/O I/O I/O Power supply for Audio output Ground for Audio output Test monitor output 2 Power supply 3 for digital circuits Ground 2 for digital circuits Expansion I/O port 0 Expansion I/O port 1 Expansion I/O port 2
Function
EXT1
*EXT2
MCLK MDATA MLD
*
Microcontroller command clock signal input Microcontroller command data signal input Microcontroller command load signal input Status signal output Subcode block clock signal output 4.2336 MHz / 8.4672 MHz clock signal output 88.2 kHz clock signal output Digital audio interface signal output Flag signal output LSI reset signal input Test mode setting input Ground 3 for digital circuits Crystal oscillator circuit input Crystao oscillator circuit output Power supply 2 for digital I/O Power supply 2 for internal digital circuits DRAM data signal I/O 2 DRAM data signal I/O 1 DRAM data signal I/O 0 DRAM data signal I/O 3 DRAM data signal I/O 4 DRAM data signal I/O 5 DRAM data signal I/O 6 DRAM data signal I/O 7
STAT
*BLKCK *SMCK *PMCK *TX *FLAG
NRST NTEST DVSS3 X1 X2 IOVDD2 DVDD2 D2 D1 D0 D3 D4 D5 D6 D7
Note) Pins marked with an asterisk can be switched to different signals by using microcontroller commands.
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Pin Descriptions (continued)
Pin No. 96 97 98 99 100 Symbol D15 D14 DRVDD2 D13 D12 I/O I/O I/O I I/O I/O DRAM data signal I/O 15 DRAM data signal I/O 14 Power supply 2 for DRAM interface I/O DRAM data signal I/O 13 DRAM data signal I/O 12 Function
Note) Pins marked with an asterisk can be switched to different signals by using microcontroller commands. The specifications of the DRAM pins depend on their type and capacitance.
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Absolute Maximum Ratings
Parameter
Ta = 25C2C
Rating Unit Note DVSS1, 2, 3 = 0 V AVSS = 0 V LOVSS1, 2 = 0 V DVSS1, 2 = 0 V AVSS1, 2 = 0 V LOVSS1, 2 = 0 V DVSS1, 2, 3 = 0 V AVSS = 0 V LOVSS1, 2 = 0 V DVSS1, 2, 3 = 0 V AVSS = 0 V LOVSS1 = 0 V DVSS1, 2, 3 = 0 V AVSS = 0 V LOVSS1, 2 = 0 V
Symbol DRVDD1, 2 IOVDD1, 2 AVDD LOVDD1, 2 DVDD1, 2, 3
A1
Supply voltage
- 0.3 to + 4.6
V
A2
Internal supply voltage
- 0.3 to + 2.0 DVSS1, 2, 3 - 0.3 to DRVDD1, 2 + 0.3 (Upper limit: 4.6 V) DVSS1, 2, 3 - 0.3 to IOVDD1, 2 + 0.3 (Upper limit: 4.6 V) AVSS - 0.3 to AVDD + 0.3 (Upper limit: 4.6 V) LOVSS1, 2 - 0.3 to LOVDD1, 2 + 0.3 (Upper limit: 4.6 V) DVSS1, 2, 3 - 0.3 to DRVDD1, 2 + 0.3 (Upper limit: 4.6 V) DVSS1, 2, 3 - 0.3 to IOVDD1, 2 + 0.3 (Upper limit: 4.6 V) AVSS - 0.3 to AVDD + 0.3 (Upper limit: 4.6 V) LOVSS1, 2 - 0.3 to LOVDD1, 2 + 0.3 (Upper limit: 4.6 V) 560
V
A3
Input voltage
VI
V
A4
Output voltage
VO
V
A5
Power dissipation Operating ambient temperature Storage temperature
PD
mW C C
A6 A7
Note) 1. 2. 3. 4. 5.
TOPR TSTG
- 30 to + 85 - 50 to + 125
The absolute maximum ratings are the limit values beyond which the IC may be broken. They do not assure operations. Connect each of the DVSS1 , DVSS2 , DVSS3 , AVSS and LOVSS1, 2 pins directly to ground and use at the same voltage. Connect each of the DRVDD1 , DRVDD2 , IOVDD1 , IOVDD2 , AVDD and LOVDD1, 2 pins directly to the specified power supply and use at the same voltage. DRVDD , IOVDD1 , IOVDD2 , AVDD1 and AVDD2 should be powered up at the same time before power up the DVDD1 , DVDD2 , DVDD3 pins at the same time when not using an internal regulator. Connect a bypass capacitor of 0.1 F or larger between each of the power supply pins and ground.
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Operating Supply Voltage Range
Parameter B1 B2 B3 B4 B5 B6 I/O system supply voltage Digital system supply voltage Analog system supply voltage Audio system 1 supply voltage Audio system 2 supply voltage D-RAM interface voltage
Ta = -30C ~ +85C, DVSS1, 2, 3 = 0 V, AVSS = 0 V, LOVSS1, 2 = 0 V
Limits Symbol IOVDD1, 2 DVDD1, 2, 3 AVDD LOVDD1 LOVDD2 DRVDD1, 2 Conditions Min 2.2 1.35 2.4 2.4 2.0 2.2 Typ 3.3 1.5 3.3 3.3 2.5 3.3 Max 3.6 1.65 3.6 3.6 3.6 3.6 V V V V V V Unit
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Operating Supply Voltage Range (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
Limits Parameter Self-excited Oscillation 1 *1 B7 B8 B9 B10 B11 Oscillator frequency Recommended external capacitance 1 Recommended external capacitance 2 Recommended external feedback resistance Recommended external dumping resistance fxtal C1 C2 16.9344 MHz Oscillator *2 R1 Rd 1 470 M 16.9344 15 pF 15 MHz Symbol Conditions Min Typ Max Unit
Self-excited Oscillation 2 *1 B12 B13 B14 B15 B16 Oscillator frequency Recommended external capacitance 1 Recommended external capacitance 2 Recommended external feedback resistance Recommended externaldumping resistance fxtal C1 C2 33.8688 MHz Oscillator *3 R1 Rd 1 100 M 33.8688 15 pF 15 MHz
Note) *1: Oscillation circuit
CSTCE16M9V53, CSTCG33M8V53
Rd X2 MN662793CF X1
C2
Oscillator
R1 C1
*2: Values for C1 and C2 specified above are standard values when use CSTCE16M9V53 made in Murata Manufacturing Co., Ltd. as an oscillator. However, CSTCE16M9V53 builds in C1 and C2 of the above standard value. The appropriate capacitors' values differ according to the oscillator used. Use the values specified by the oscillator manufacturer. *3: Values for C1 and C2 specified above are standard values when use CSTCG33M8V53 made in Murata Manufacturing Co., Ltd. as an oscillator. However, CSTCG33M8V53builds in C1 and C2 of the above standard value. The appropriate capacitors' values differ according to the oscillator used. Use the values specified by the oscillator manufacturer.
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Electrical Characteristics DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(1) DC Characteristics Limits Parameter C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 Supply current I/O / analog system supply current Audio system 2 current Total power consumption Supply current I/O / analog system supply current Audio system 2 current Total power consumption Supply current I/O / analog system supply current Audio system 2 current Total power consumption Supply current I/O / analog system supply current Audio system 2 current Total power consumption Symbol IDD IDD(A, L1) IDD(L2) PT IDD IDD(A, L1) IDD(L2) PT IDD IDD(A, L1) IDD(L2) PT IDD IDD(A, L1) IDD(L2) PT Conditions Min Anti-shock memory function used. No external load connected. (in 2x-speed playback mode) ADPCM compression: ON MP3 decode: OFF CD-ROM decode: OFF Digital PLL: OFF Anti-shock memory function used. No external load connected. (in 4x-speed playback mode) MP3 decode: ON CD-ROM decode: ON Digital PLL: OFF Anti-shock memory function used. No external load connected. (in 4x-speed playback mode) WMA decode: ON CD-ROM decode: ON Digital PLL: OFF Anti-shock memory function used. No external load connected. (in 8x-speed playback mode) MP3 decode: OFF CD-ROM decode: OFF Digital PLL: OFF Typ 22 12 8 92.6 24 14 2 102.2 25 16 8 110.3 24 16 8 108.8 Max 65 24 20 227 70 28 20 247 75 32 20 278 70 32 20 261 mA mA mA mW mA mA mA mW mA mA mA mW mA mA mA mW Unit
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Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(1) DC Characteristics (continued) Limits Parameter Input Pins 1 C17 C18 C19 DRVDD voltage type Symbol Conditions Min Typ Max Unit
D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15 VIH1 VIL1 ILK1 VIN = 0 V or 3.3 V 2.31 0.0 3.30 0.99 1 V V A
High-level input voltage Low-level input voltage Input leakage current IOVDD voltage type
Input Pins 2 C20 C21 C22
EXT0, EXT1, EXT2, MCLK, MDATA, MLD, NRST, TEST VIH2 VIL2 ILK2 VIN = 0 V or 3.3 V 2.31 0.0 3.30 0.99 1 V V A
High-level input voltage Low-level input voltage Input leakage current AVDD voltage type
Input Pins 3 C23 C24 C25
NRFDET, OFT , BDO, PWMSEL VIH3 VIL3 ILK3 VIN = 0 V or 3.3 V 2.31 0.0 3.30 0.99 1 V V A
High-level input voltage Low-level input voltage Input leakage current
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Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(1) DC Characteristics (continued) Limits Parameter Symbol Conditions Min Typ Max Unit
Output Pins 1 DRVDD voltage type D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15, A0, A1, A2, A3, A4, A5, A6, A7, A8, A9, A10, A11, UDQM, LDQM, SDRCK, NWE, NCAS, NRAS, NCS C26 C27 High-level output voltage Low-level output voltage DRVDD voltage type VOH1 VOL1 IOH1 = - 1.0 mA IOL1 = 1.0 mA 2.7 0.4 V V
Output Pins 2 C28 C29 C30
BA0, BA1 VOH2 VOL2 OLK2 IOH2 = - 1.0 mA IOL2 = 1.0 mA Hi-Z state VO = 0 V or 3.3 V 2.7 0.4 1 V V
High-level output voltage Low-level output voltage Output leakage current IOVDD voltage type
Output Pins 3 C31 C32
SPPOL, TRVM, TRM, FOM, STAT, TX VOH3 VOL3 IOH3 = - 1.0 mA IOL3 = 1.0 mA 2.7 0.4 V V
High-level output voltage Low-level output voltage
Output Pin 4 IOVDD voltage type SPOUT, TRVP, TRVP2, TRVM2, TRP, FOP, TMON1, TMON2, EXT0, EXT1, EXT2, BLKCK, SMCK, PMCK, FLAG C33 C34 C35 High-level output voltage Low-level output voltage Output leakage current AVDD voltage type VOH4 VOL4 OLK4 LDON VOH5 VOL5 OLK5 IOH5 = - 1.0 mA IOL5 = 1.0 mA Hi-Z state VO = 0 V or 3.3 V 2.7 0.4 1 V V A IOH4 = - 1.0 mA IOL4 = 1.0 mA Hi-Z state VO = 0 V or 3.3 V 2.7 0.4 1 V V A
Output Pins 5 C36 C37 C38
High-level output voltage Low-level output voltage Output leakage current
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Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(1) DC Characteristics (continued) Limits Parameter Analog System Input Pin 1 C39 Input current ARF VARF EFM signal input level in an application circuit of DSL block. REGSEL: R1 + R2 + R3 setting Internal resistance between ARF and DSLF pins REGSEL: R2 + R3 setting RARF REGSEL: R3 setting REGSEL: R1 + R2 + R3 and RFSW = ON setting Analog System Input Pin 3 C42 C43 TE, FE, RFENV, ADPVCC VIH4 VIL4 NTEST2 VIH5 VIL5 ILK5 1.75 0.00 2.50 0.75 1.0 V V A 0.33 2.97 V V 0.5 65 26 13 32 1.0 100 40 20 50 135 54 27 68 k V[P-P] IREF IREF When pulled up with an 82-k resistor. 18 29 41 A Symbol Conditions Min Typ Max Unit
Analog System Input Pin 2 C40 nput signal amplitude
C41
High-level input voltage Low-level input voltage
LOVDD2 System Input Pin 5 C44 C45 C46
High-level input voltage Low-level input voltage Input leakage current
A/D Converter (for servo) C47 C48 C49 Resolution Integral nonlinearity Differential nonlinearity RES INL DNL A/D output = 99 to 66 (2's complement) 8 2 3 LSB bit
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Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(1) DC Characteristics (continued) Limits Parameter Analog System Output Pin 1 C50 C51 C52 Output current (N) Output current (P) Output unbalance current Symbol Conditions Min DSLF (IREF pin is pulled up to AVDD with an 82 k resistor) IDSH IDSH IDSEL BDO: Low, Tracking ON state DSLF = 1.65 V BDO: Low, Tracking ON state DSLF = 1.65 V BDO: Low, Tracking ON state Normal current mode 56 - 104 -7 80 - 80 0 104 - 56 7 A Typ Max Unit
Analog System Output Pin 2 C53 Phase comparator output current (N)
PLLF (IREF pin is pulled up to AVDD with an 82 k resistor) IPFH IPFH ILKP IPLBL fVCO1 PLLF = 1.65 V 56 80 104
C54 C55 C56 C57
Phase comparator output current (P) Input leakage current Output unbalance current VCO oscillator frequency for PLL
PLLF = 1.65 V Hi-Z state PLLF = 1.65 V
- 104
- 80
- 56 1
A
- 10 25.9
0
10 103.7 MHz
Analog System Output Pin 3 C58 C59 C60 Output current (N) Output current (P) Input leakage current
PLLFO (IREF pin is pulled up to AVDD with an 82 k resistor) IPFHO IPFHO ILKPO Hi-Z state 59 - 111 85 - 85 111 - 59 1 A
Analog System Output Pin 4 C61 C62 Output current (N) Output current (P)
TBAL, FBAL (IREF pin is pulled up to AVDD with an 82 k resistor) IBAH IBAL At default setting (x 1) At default setting (x 1) 15 - 29 22 - 22 29 - 15 A
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Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(1) DC Characteristics (continued)
Recommended Circuit for DSL and PLL Blocks (AVDD = 3.3V)
Note) The above is a basic circuit. Calculate the constants and other factors of the circuit in consideration of playability when making use of this circuit for actual applications.
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Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(1) DC Characteristics (continued)
Recommended Circuit for DSL and PLL Blocks (AVDD = 2.4 V)
Note) The above is a basic circuit. Calculate the constants and other factors of the circuit in consideration of playability when making use of this circuit for actual applications.
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Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(1) DC Characteristics (continued) Limits Parameter Symbol Conditions Min D/A Converter Analog Characteristics C63 C64 C65 C66 C67 Signal-to-noise ratio Dynamic range Total harmonic distortion ratio Crosstalk Output level 1 S/N D. R. THD + N EIAJ EIAJ EIAJ EIAJ 1 kHz F. S. *1 Difference between OUTL and OUTR pins at output level 20 log (VR / VL) 1 kHz F.S. *2 80 1.04 90 86 97 94 0.005 85 1.33 1.62 0.009 dB dB % dB V[rms] Typ Max Unit
C68
Output level difference
- 0.99
+ 0.99
dB
C69
Output level 2
0.69
0.88
1.07
V[rms]
Note) 1. The analog characteristics show the measured values when inserting a 15 0 resistor between LOVDD1 and power supply. The analog characteristics is prescribed when LOVDD1 voltage is 3.3V. The above typical values are only reference values and not guaranteed. 2. With no anti-shock memory function used, the operation of the D/A converter will not be guaranteed in modes other than normal-speed playback. 3. *1: The output level 1 shows the measured value at the output pin of the application circuit below. *2: The output level 2 shows a value at the output pin of the IC and is calculated by taking the measured value of output level 1, dividing it by the circuit gain.
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Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(2) AC Characteristics Limits Parameter Reset Timing *1 C70 NRST pulse width TNRSTL 200 s Symbol Conditions Min Typ Max Unit
Power Supply Ripple Noise *2 C71 C72 Ripple amplitude Ripple noise amplitude VRIP VNZ 15 30 mV[p-p] mV[p-p]
Note) *1: When the power is turned on, reset with the NRST pulse which is equal to or exceeds the above pulse width only after the clock oscillation is stabilized within 10% of error of the specified oscillator frequency. Keep noise on the reset line as low as possible.
TNRSTL NRST 0.2 VDD 0.2 VDD
*2: The standard ripple noise values of the IC are guaranteed on condition that the values apply to typical 50-Hz to 100-Hz ripples with 500 kHz typical noise and that both the ripples and noise are in sine waveform as shown below. The values, however, vary under the influence of other parts located on the PCB. Therefore, be sure to apply the IC to practical applications and check the actual ripple noise values.
Noise frequency: 500 kHz
VNZ VRIP Ripple frequency: 50 Hz to 100 Hz
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Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(2) AC Characteristics (continued) Limits Parameter Transition Time 1 C73 C74 Rise time Fall time SBCK, TXTCK TR2 TF2 50 50 ns ns MCLK, MLD TR1 TF1 250 250 ns ns Symbol Conditions Min Typ Max Unit
Transition Time 2 * C75 C76 Rise time Fall time
0.7 IOVDD 0.3 IOVDD
0.7 IOVDD 0.3 IOVDD
TR1, 2
TF1, 2
Note) *: SBCK and TXTCK are output from EXT1.
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MN662793
Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(2) AC Characteristics (continued) Limits Parameter Symbol Conditions Min Microcontroller Command Input Timing C77 C78 C79 C80 C81 C82 C83 Clock frequency Clock pulse width Data setup time Data hold time MLD delay time Latch pulse time MCLK delay time fMCLK TCH,CL TDSU TDH TLDD TLDW TCKD 150 150 150 150 0.5 300 10 2 MHz ns ns ns ns s ns Typ Max Unit
1/fMCLK
MCLK TCH TCL
MDATA
TDSU
TDH
MLD
TLDD
TLDW
TCKD
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MN662793
Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(2) AC Characteristics (continued) Limits Parameter Sub code Interface *1 C84 C85 C86 C87 C88 Clock width High-level pulse width Low-level pulse width Delay time Setup delay time Symbol SBCK, SUBC, TXNCLDCK TCK TCKH TCKL When digital filter is used. *2 TSBD TSD When no filter is used. *2 909 400 400 350 173 150 ns ns ns ns ns ns Conditions Min Typ Max Unit
TCK TCKL SBCK
TCKH
SUBC
TSD TXNCLDCK
TSBD
Note) *1: SBCK is output from EXT1, SUBC is output from EXT0, and TXNCLDCK is output from EXT2. *2: SBCK,TXTCK noise filter command is SBCKNF (by setting the D5 and D4 bits of the 67 command) .
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MN662793
Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(2) AC Characteristics (continued) Limits Parameter Subcode Interface C89 C90 C91 C92 C93 Symbol Conditions Min TXTCK, TXTD, DQSY TCK TCKH TCKL TSBD TSD 2500 1200 1200 1150 1100 ns ns ns ns ns Typ Max Unit
Clock frequency High-level pulse width Low-level pulse width Delay time Setup delay time
TCK TCKH
TXTCK TCKL
TXTD
TSD
TSBD
DQSY
Note) 1. TXTCK is input or output from EXT1, TXTD is input or output from EXT0, and DQSY is input or output from EXT2. 2. The cycle width of the readout clock TXTCK is proportional to disc rotation speed. High-speed readout such as high-speed CLV playback or high-speed jitter-free playback using MSON (Memory system setting) is possible. Example) When in 2x speed mode TSBD2 = 450 ns (Typ.)
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MN662793
Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(2) AC Characteristics (continued) Limits Parameter Symbol Conditions Min STAT Output Interface (When analog filter 1 is used.) C94 C95 C96 C97 Clock width High-level pulse width Low-level pulse width Delay time TMT TMTH TMTL TMTD 909 300 300 225 ns ns ns ns Typ Max Unit
STAT Output Interface (When analog filter 2 is used.) C98 C99 C100 C101 Clock width High-level pulse width Low-level pulse width Delay time TMT TMTH TMTL TMTD 500 220 220 200 ns ns ns ns
STAT Output Interface (When no noise filter is used.) C102 C103 C104 C105 Clock width High-level pulse width Low-level pulse width Delay time TMT TMTH TMTL TMTD
TMT TMTL MCLK TMTH
500 220 220 173
ns ns ns ns
STAT
TMTD
Note) 1. In multiple-byte read mode using REGRD command (96h), VWA_ID command (97h), or VWAIDRD command (98h), it is necessary to set the high-level pulse width TMTH to more than 450 ns in 1-byte increments. 2. MCLK,MDATA,MLD noise filter command is MCIFNF (by setting the D5 and D4 bits of the 67 command) .
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MN662793
Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(2) AC Characteristics (continued) Limits Parameter D/A Output Interface 1 C106 C107 C108 C109 C110 Clock width High-level pulse width Low-level pulse width Setup time Hold time TBCLK TBCLKH TBCLKL TST THD In normal-speed playback mode (64fs) 70 70 354 177 177 Ns Ns Ns Ns Ns Symbol Conditions Min Typ Max Unit
D/A Output Interface 2 C111 C112 C113 C114 C115 Clock width High-level pulse width Low-level pulse width Setup time Hold time TBCLK TBCLKH TBCLKL TST THD In 4x-speed playback mode (48fs) 30 30 118 59 59 Ns Ns Ns Ns Ns
D/A Output Interface 3 C116 C117 C118 C119 C120 Clock width High-level pulse width Low-level pulse width Setup time Hold time TBCLK TBCLKH TBCLKL TST THD
TBCLK TBCLKL TBCLKH
59 29.5 In 8x-speed playback mode (48fs) 15 15 29.5
Ns Ns Ns Ns Ns
D/A Output Interface
BCLK
SRDATA LRCK TST THD
Note) SRDATA, BCLK, and LRCK are output in combination with PMCK (BCLK), FLAG (SRDATA), and SMCK (LRCK) or EXT0 (SRDATA), EXT1 (LRCK), and EXT2 (BCLK).
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MN662793
Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(2) AC Characteristics (continued) Limits Parameter Symbol Conditions Min D/A Converter Input Timing 1 (When no noise filter is used.) C121 C122 C123 C124 C125 C126 BCLK frequency SCLK pulse width Data setup time Data hold time LRCK frequency BCLK-LRCK timing fBCLK TCH,CL TDSU TDH fLRCK TBL,TLB 100 100 100 100 44.1 2.8 Ns Ns Ns Ns KHz Ns Typ Max Unit
D/A Converter Input Timing 2 (When digital filter is used.) C127 C128 C129 C130 C131 C132 BCLK frequency SCLK pulse width Data setup time Data hold time LRCK frequency BCLK-LRCK timing fBCLK TCH,CL TDSU TDH fLRCK TBL,TLB 100 150 100 100 44.1 2.8 Ns Ns Ns Ns KHz Ns
1/fBCLK
BCLKIN TCH SRDATAIN TDSU TDH LRCKIN TBL TLB TBL TLB TCL
1/fLRCK
Note) 1. SRDATAIN,BCLK,LRCK noise filter command is SRDATANF (by setting the D7 and D6 bits of the 67 command) . 2. SRDATAIN, LRCKIN, and BCLKIN are input from EXT0 (SRDATAIN), EXT1 (LRCKIN), and EXT2 (BCLKIN) respectively.
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MN662793
Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(2) AC Characteristics (continued) Parameter In BCKSEL = 0 mode Limits Symbol Conditions Min EDO, First-Page DRAM Interface Read / Write Cycle C133 C134 C135 A0 to A11 row address setup time A0 to A11 row address hold time A0 to A11 column address setup time A0 to A11 column address hold time RAS-CAS delay time (NCAS0, NCAS1) RAS access time CAS access time Write enable signal NWE setup time Write enable signal NWE hold time D0 to D15 write data setup time D0 to D15 write data hold time tASR tRAH tASC tCAH tRCD tRAC tCAC tWCS tWCH tDWDS tDWDH 2 1 1 cycle cycle cycle Typ Max Unit
C136
2
cycle
C137 C138 C139 C140
2 4 2 2
cycle cycle cycle cycle
C141 C142 C143
2 1 2
cycle cycle cycle
EDO, First-Page DRAM Interface Page Mode Data Transfer C144 C145 C146 CAS pre-charge pulse width CAS low-level pulse width RAS hold time tCP tCAS tRSH 1 2 2 cycle cycle cycle
EDO, First-Page DRAM Interface CAS Before RAS Refresh C147 C148 CAS-RAS delay time Refresh RAS low-level pulse width Refresh CAS low-level pulse width tCRD tRRAS tRCAS 1 4 cycle cycle
C149
5
cycle
Note) One cycle is the system clock cycle of 1 / (16.9344 MHz or 33.8688 MHz) [s]. The system clock frequencies, 16.9344 MHz and 33.8688 MHz, are determined according to the DCKSEL command (65h command D6 and D5).
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MN662793
Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(2) AC Characteristics (continued) Parameter In BCKSEL = 1 mode Limits Symbol Conditions Min EDO, First-Page DRAM Interface Read / Write Cycle C150 C151 C152 A0 to A11 row address setup time A0 to A11 row address hold time A0 to A11 column address setup time A0 to A11 column address hold time RAS-CAS delay time (NCAS0, NCAS1) RAS access time CAS access time Write enable signal NWE setup time Write enable signal NWE hold time D0 to D15 write data setup time D0 to D15 write data hold time tASR tRAH tASC tCAH tRCD tRAC tCAC tWCS tWCH tDWDS tDWDH 2 1 1 cycle cycle cycle Typ Max Unit
C153
1
cycle
C154 C155 C156 C157
2 4 1 2
cycle cycle cycle cycle
C158 C159 C160
1 1 1
cycle cycle cycle
EDO, First-Page DRAM Interface Page Mode Data Transfer C161 C162 C163 CAS pre-charge pulse width CAS low-level pulse width RAS hold time tCP tCAS tRSH 1 1 1 cycle cycle cycle
EDO, First-Page DRAM Interface CAS Before RAS Refresh C164 C165 CAS-RAS delay time Refresh RAS low-level pulse width Refresh CAS low-level pulse width tCRD tRRAS tRCAS 1 4 cycle cycle
C166
5
cycle
Note) One cycle is the system clock cycle of 1 / (16.9344 MHz or 33.8688 MHz) [s]. The system clock frequencies, 16.9344 MHz and 33.8688 MHz, are determined according to the DCKSEL command (65h command D6 and D5).
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MN662793
Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(2) AC Characteristics (continued) EDO, First-Page DRAM Access Timing (NRAS, NCAS0, NCAS1, NWE, A0 to A11, D0 to D15) (Normal mode)
A11 to A0
Row Address
Column Address tASC tCAH
tASR
NRAS
tRAH
NCAS0*C NCAS1
tRCD
[READ] NEW (** H)
D15 to D0 tRAC tCAC [WRITE] NWE tWCS D15 to D0 tDWDS tDWDH tWCH
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MN662793
Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(2) AC Characteristics (continued) EDO, First-Page DRAM Access Timing (NRAS, NCAS0, NCAS1, NWE, A0 to A11, D0 to D15) (Page mode) A11 to A0 Row Address Column Address Column Address Column Address
tASC
NRAS
tCAH
tRSH NCAS0 NCAS1 tCP tCAS
[READ] NEW ( H)
D15 to D0
tCAC
[WRITE] NWE
D15 to D0 tDWDS tDWDH
(CAS Before RAS Refresh Mode) NRAS tCRD NCAS0 NCAS1 tRCAS tRRAS
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MN662793
Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(2) AC Characteristics (continued) Limits Parameter SDRAM Interface C167 C168 C169 C170 C171 C172 C173 C174 C175 C176 C177 C178 C179 C180 C181 C182 SDRCK cycle time SDRCK high-level pulse width SDRCK low-level pulse width NCS input setup time NCS input hold time NRAS input setup time NRAS input hold time NCAS input setup time NCAS input hold time New input setup time New input hold time LDQM, UDQM input setup time LDQM, UDQM input hold time D0 to D15 input setup time D0 to D15 input hold time A0 to A11, BA0,BA1 input setup time A0 to A11, BA0, BA1 input hold time tCLK tCH tCL tCSS tCSH tRAS tRAH tCAS tCAH tWES tWEH tDMS tDMH tDQS tDQH tAS tAH 1 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 1 1 1 cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle cycle Symbol Conditions Min Typ Max Unit
C183
1
cycle
Note) 1. One cycle is the system clock cycle of 1 / (16.9344 MHz or 33.8688 MHz) [s]. 2. Connect SDRAM near this LSI as much as possible. Connect the wiring load of the SDRCK pin specially within 5pF.
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MN662793
Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(2) AC Characteristics (continued) Limits Parameter SDRAM Interface C184 C185 C186 access time from SDRCK Hi-Z output time from SDRCK low impedance output time from SDRCK high impedance output time from SDRCK tAC tOH tOLZ tOHZ 0 0 15 ns ns ns Symbol Conditions Min Typ Max Unit
C187
0
ns
Note) One cycle is the system clock cycle of 1 / (16.9344 MHz or 33.8688 MHz) [s].
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MN662793
Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(2) AC Characteristics (continued) SDRAM Access Timing (SDRCK, NCS, NCAS, NWE, LDQM, UDQM, A0 to A11, BA0, BA1, D0 to D15)
[WRITE] SDRCK
tCLK
tCH
tCL
tCSS
NCS
tCSH
tRAS
NRAS
tRAH tCAS tCAH
NCAS
tWES tWEH
NWE
tDMS
UDQM
tDMH
tDMS
LDQM
tDMH
tDQS
D0 to D15 VALID
tDQH
tAS
A0 to A11, BA0, BA1
tAH
RAS address
tAS
tAH
CAS address
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MN662793
Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(2) AC Characteristics (continued) SDRAM Access Timing (continued) (SDRCK, NCS, NCAS, NWE, LDQM, UDQM, A0 to A11, BA0, BA1, D0 to D15)
[READ] SDRCK
tCLK
tCH
tCL
tCSS
NCS
tCSH
tRAS
NRAS
tRAH tCAS tCAH tDMH
NCAS
tDMS
UDQM
tWES tWEH
tDMS
LDQM
tDMH
tAC tOLZ
D0 to D15
Output decision
tOHZ tOH
tAS
A0 to A11, BA0, BA1
tAH
tAS
tAH
RAS address
CAS address : Invalid data
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SDRAM Initialize Sequence (SDRCK, NCS, NCAS, NWE, A0 to A11, BA0, BA1)
MN662793
Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(2) AC Characteristics (continued) SDRAM Initialize Sequence (SDRCK, NCS, NCAS, NWE, A0 to A11, BA0, BA1)
PALL
REF
REF
..........
REF
MRS
16 refresh 10 cycle to 15 cycle NRST 6 cycle 6 cycle
SDRCK
NCS
NRAS
NCAS
NWR
BA0,BA1
A0 to A11
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MN662793
Electrical Characteristics (continued) DVDD1, 2, 3 = 1.5 V, DRVDD1, 2 = 3.3 V, IOVDD1, 2 = 3.3 V, DVSS1, 2, 3 = 0 V, AVDD = 3.3 V, AVSS = 0 V, LOVDD1 = 3.3 V, LOVDD2 = 2.5 V, LOVSS1, 2 = 0 V
(2) AC Characteristics (continued)
SDRAM Page Access Timing (SDRCK, NCS, NRAS, NCAS, NWE, A0 to A11, BA0, BA1)
Row Address SDRCK Column Address Column Address .... Precharge
NCS
NRAS
NCAS
UDQM
LDQM
A0 to A11, BA0, BA1
RAS address
CAS address1
CAS address2
[WRITE] NWE
D0 to D15
VALID1
VALID2
[READ] NWE
D0 to D15
VALID1
VALID2
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Request for your special attention and precautions in using the technical information and semiconductors described in this material
(1) An export permit needs to be obtained from the competent authorities of the Japanese Government if any of the products or technical information described in this material and controlled under the "Foreign Exchange and Foreign Trade Law" is to be exported or taken out of Japan. (2) The technical information described in this material is limited to showing representative characteristics and applied circuits examples of the products. It neither warrants non-infringement of intellectual property right or any other rights owned by our company or a third party, nor grants any license. (3) We are not liable for the infringement of rights owned by a third party arising out of the use of the technical information as described in this material. (4) The products described in this material are intended to be used for standard applications or general electronic equipment (such as office equipment, communications equipment, measuring instruments and household appliances). Consult our sales staff in advance for information on the following applications: * Special applications (such as for airplanes, aerospace, automobiles, traffic control equipment, combustion equipment, life support systems and safety devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. * Any applications other than the standard applications intended. (5) The products and product specifications described in this material are subject to change without notice for modification and/or improvement. At the final stage of your design, purchasing, or use of the products, therefore, ask for the most up-to-date Product Standards in advance to make sure that the latest specifications satisfy your requirements. (6) When designing your equipment, comply with the guaranteed values, in particular those of maximum rating, the range of operating power supply voltage, and heat radiation characteristics. Otherwise, we will not be liable for any defect which may arise later in your equipment. Even when the products are used within the guaranteed values, take into the consideration of incidence of break down and failure mode, possible to occur to semiconductor products. Measures on the systems such as redundant design, arresting the spread of fire or preventing glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (7) When using products for which damp-proof packing is required, observe the conditions (including shelf life and amount of time let standing of unsealed items) agreed upon when specification sheets are individually exchanged. (8) This material may be not reprinted or reproduced whether wholly or partially, without the prior written permission of Matsushita Electric Industrial Co., Ltd.
2003 SEP

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